As a parallel test, employing a testing device, a line mode test for semiconductor devices has become known (see for example the non-patent publication 1). First, the line mode test is briefly explained. FIG. 13 shows the structure of a semiconductor storage device disclosed in the non-patent publication 1. The storage device shown in FIG. 13 includes a multi-purpose register MPR (write/expectation value register) 1101 and a comparator circuit 1102 for complementary sub-IO lines SIO_T, SIO_B (bit line pair). The comparator circuit 1102 is formed by an Ex-OR circuit, and an output signal (coincidence detection signal) MATCH is wired-OR connected. The multi-purpose register MPR 1101, comprising a flip-flop formed by cross-connection of an output and an input of an inverter composed of a P-channel MOS transistor P41 and an N-channel MOS transistor N49 and an inverter composed of a P-channel MOS transistor P42 and an N-channel MOS transistor N50, is connected across a main I/O line pair (MIOT, MIOB) and a sub I/O line pair (SIO_T, SIO_B), in order to perform copy/write in a line mode test (LMT) and parallel comparison by line read. During the time of activation of the multi-purpose register MPR (write/expectation register) 1101, the power supply potential and the ground potential are supplied to CRE_B and CRE_T of the multi-purpose register MPR (write/expectation value register) 1101.
During the line mode test, test data are written in the multi-purpose register MPR (write/expectation value register) 1101, in which a random patterns possible on one line. The random pattern data are simultaneously written in the memory cells connected to the selected word line. A signal TR is in a high level, while a test compare trigger signal COMP is in a low level. The complementary data of the main IO lines MIOT, MIOB are stored in the flip-flop of the multi-purpose register MPR (write/expectation value register) 1101, and transmitted to the complementary sub-IO lines SIO_T, SIO_B via the N-channel MOS transistors N41, N42 in the on-state so as to be written in the memory cells connected to the selected word line.
When the test compare trigger signal COMP is in a high level and the signal TR is in a low level, parallel comparison is carried out in each comparator 1102 to detect coincidence between the readout data and the expectation data. Specifically, the N-channel MOS transistors N41, N42 are off, while the N-channel MOS transistors N43, N44 are on. When MIOT and MIOB as write data are in the high level and in the low level, respectively, the N-channel MOS transistor N46, the gate of which is supplied with a value held by the multi-purpose register MPR (write/expectation value register) 1101 is turned on, while the N-channel MOS transistor N45 is turned off. When the sub-IO line SIO_B, transmitting the readout data, is high (in case of failure), the N-channel MOS transistor N48 is turned on, with the coincidence detection signal MATCH being in the low level (error detected). When the sub-IO line SIO_B is low, the N-channel MOS transistor N48 is turned off, with the coincidence detection signal MATCH being in the high level. In case of writing with the main IO lines MIOT, MIOB being in the low level and in the high level, respectively, the N-channel MOS transistor N45 is turned on to detect an error in similar manner. If even only one of plural comparators, connecting to the signal line MATCH, is non-coincident, an error signal is sent out from MATCH and output to an output terminal DQ, not shown. Any failure on a line is detected by one read cycle.
As a modification of the line mode test, there is also known a structure in which write data and expectation data are directly supplied from a write bus (see for example the Patent Publication 1). In this conventional semiconductor storage device, the data read out from each selected one of plural columns is compared to expectation data by test means and the result of comparison is output. The test means for conducting a test on plural columns is provided common to the columns. Specifically, as shown in FIG. 14 hereof (corresponding to FIG. 2 of the Patent Publication 1), a first differential amplifier 60 is connected to bit line pairs BL, /BL. There are provided write buses W, /W, readout buses R, /R and a readout/test circuit 7. During a test, a column decoder 4 compares the data read out from every other bit line pair of plural bit line pairs BL, /BL to a given expectation data and respective results of comparison are output. The column decoder 4 then compares the remaining ones of the bit line pairs BL, /BL to a given expectation to output respective results of comparison. The readout/test circuit 7 includes a switch 71 connected across the readout buses R, /R and data buses DB, /DB, a switch 72 connected across the readout buses R, /R and buses for line test LB, /LB, a differential amplifier 73 connected to the data buses DB, /DB, an expectation data write circuit 74 connected to the buses for line test LB, /LB, and an error detection circuit 75 connected to the buses for line test LB, /LB, and outputs an error flag EF if an error is detected during the line mode test.
There is also known a structure including a coincidence detection circuit supplied with readout data from plural cell arrays to detect possible coincidence of the input data to compress 16 IO to 4 IO (see for example the Patent Publication 2).
The structure shown in the block diagram of FIG. 15 is that of a conventional test circuit of the semiconductor device described in the aforementioned Patent Publication 2, in which no expectation data is needed during reading. That is, data may be independently written in a write amplifier of each memory cell, in order to test data interference between neighboring memory cells. That is, first to fourth read/write amplifiers (Ramp and Wamp) 1302 are provided as peripherals of a memory cell array 1301. The memory cell array 1301 includes an X-decoder 1304, supplied with and decoding an X-address to select a word line, a sense amplifier 1305 connected to the bit line and a column decoder 1306 supplied with and decoding a Y-address to select a bit line. These elements as one unit are also termed a ‘mat’ or a ‘cell array block’. In FIG. 15, the X-decoder 1304 may be provided common to plural cellblocks.
A first write data bus, a second write data bus, a third write data bus and a fourth write data bus are connected common to each of the first write amplifiers (Wamp), second write amplifiers (Wamp), third write amplifiers (Wamp) and the fourth write amplifiers (Wamp) of each of the four memory cell arrays 1301. During line testing, the first to fourth write amplifiers are supplied with data from the first to fourth write data buses in parallel. The data from the write amplifier (Wamp) is written in the memory cell connected to the selected word line.
FIG. 16 shows a connection structure of the circuit of FIG. 15 at the time of readout in the parallel test mode. The sense amplifier outputs of the bit lines selected by a column decoder 1306 are amplified by a read amplifier (Ramp), while four output signals output from the first read amplifiers (Ramp) of the four memory cell arrays are supplied to a first comparator 13030. In similar manner, the four output signals output from the second to fourth read amplifiers (Ramp) of the four memory cell arrays are supplied to second to fourth comparators 13031 to 13033. Each of the comparators 13030 to 13033 outputs a ‘pass’ and a ‘fail’ when the four input signals are all coincident and when any one of the signals is non-coincident, respectively. In an alternative structure, there is provided a comparator supplied with outputs of comparators 13030 to 13033 to verify the possible coincidence of the comparator outputs to compress the results of comparison.
[Non-Patent Publication 1]
K. ARIMOTO et al. “A 60-ns 3.3-V—Only 16-Mbit DRAM with Multipurpose Register”, IEEE, journal of solid-state circuits, vol. 24, No. 5, October 1989, pp 1184-1190
[Patent Publication 1]
Japanese Patent Kokai Publication No. JP-A-4-356799 (pages 5 and 6, FIGS. 1 and 2)
[Patent Publication 2]
Japanese Patent Kokai Publication No. JP-P2000-40397A (page 4, FIG. 3)